It is often desirable to use memory devices that will retain information even when the power is temporarily interrupted, or when the device is left without applied power for indefinite periods of time. A variety of semiconductor memories developed with this characteristic are known as nonvolatile memories. One category with broad application is electrically erasable and programmable read only memory (“EEPROM”). The information can be electronically stored and erased in memory cells of EEPROM. In order to assure the voltage state of a memory cell within a predetermined range after writing or erasing, verification becomes indispensable in the operation of nonvolatile memories. In particular, for a multi-level non-volatile memory in which a memory cell can store more than two states, it is important to precisely control the voltage of a memory cell after writing or erasing to perform the intended function.
Conventionally, a memory cell is programmed and verified during different periods of time. The memory cell is verified when both the word line and the bit line are at low voltage. If the threshold voltage of the memory cell has not reached a predetermined value, the word line and bit line are switched to high voltage to program (drive) the memory cell for a period of time. Each programming pulse has a fixed duration and a fixed word line voltage. After the first programming pulse, both the word line and bit line go back to low voltage and the memory cell is verified. If the memory cell fails the verification step, it is programmed again by the second programming pulse. The word line voltage either is fixed or steps up after each verification step. The memory cell is repeatedly verified and programmed until the threshold voltage of the memory cell reaches the predetermined value. The word line voltage and bit line voltage have to switch back and forth between high and low respectively for programming and verifying. Thus, the verification process is very time inefficient. Further information about this conventional verification mechanism can be found in the paper titled “Basic Feasibility Constraints for Multilevel CHE-Programmed Flash Memories,” IEEE Transactions on Electron Devices, Vol. 48, No. 9, September 2001, pages 2032–2042.
One approach to avoid frequent voltage switching on the word lines and bit lines is to verify the threshold voltage of a memory cell while the memory cell is being driven. After a memory cell is programmed for a short period of time, the threshold voltage of the memory cell begins to be verified while the memory cell is concurrently programmed while both the word line and the bit line are at high voltage. The memory cell threshold voltage is repeatedly verified during programming until the threshold voltage of the memory reaches a predetermined value.
In a read operation, the content stored in a memory cell is read out with the bit line set to a low voltage. However, the threshold voltage is read out and verified when both the word line voltage and the bit line voltage are high in the alternative approach rather than low in the conventional verification process. Thus, the reading accuracy resulting from this alternative approach is reduced as compared to conventional verification process. With high word line and bit line voltage, the cell current is higher and the parasitic resistance significantly influences the accuracy of reading the threshold voltage, which in turn adversely affects the distribution of the threshold voltage.
As shown in FIG. 1A, a nonvolatile memory includes a plurality of word lines WL1, . . . , i, i+1, . . . m, a plurality of bit lines BL1, . . . , j, j+1, . . . n, and a plurality of memory cells M(WLx, BLy). Each memory cell has a source, a drain, a control gate and a floating gate. The drain connects to a bit line. The control gate connects to a word line. In this example of a NOR-type flash memory, the N+-doped self-aligned sourced of a set of every sixteen cells connect to a common cell source signal line. FIG. 1B shows the parasitic resistance of source regions of 16 adjoining memory cells between two common cell source signal lines. These source regions generate a voltage drop when a current flows through them. For example, if the word line voltage is set to 7 volts and the bit line voltage is set to 4 volts during programming, the cell current is from around 0.15 mA to around 0.2 mA depending on the cell characteristics. Because of the source parasitic resistance, the effective gate to source voltage is also reduced. As a result, the threshold voltage actually read out of the memory cell located in the center of two common cell source signal lines is reduced by about 0.23 volts to about 0.3 volts. On the other hand, during the read operation, the bit line is at low voltage and the cell current is from about 5 μA to 20 μA. The voltage drop for the center cell is from about 7 mV to 10 mV, which is much less than the range of voltage drop (0.23–0.3 Volts) during programming. The substantial voltage drop during programming introduces inaccuracy into a verification process performed concurrently with programming.
FIG. 2 shows a threshold voltage distribution of a multi-level transistor of a four-level memory cell. The targeted threshold voltages are respectively 3, 4, 5 and 6 volts. The conventional verification mechanism can obtain a threshold voltage distribution of about 0.5 volts, which leaves a 0.5 volts margin between neighboring levels. More specifically, the first level threshold voltage distribution ranges from 2.75 to 3.25 volts with a peak at 3 volts, the second level threshold voltage distribution ranges from 3.75 to 4.25 volts with a peak at 4 volts, the third level threshold voltage distribution ranges from 4.75 to 5.25 volts with a peak at 5 volts and the fourth level threshold voltage distribution ranges from 5.75 to 6.25 volts with a peak at 6 volts. Only when the threshold voltage of a cell falls within the appropriate distribution does the memory determine that the state of the cell is correctly stored so that it can be later read out. However, for the alternative approach, if the targeted threshold voltage is 3 volts, the threshold voltage of the center cell would pass the verification when the center cell is only programmed to about 2.7 to 2.77 volts because of the voltage drop caused by the source parasitic resistance. This inaccuracy adversely affects the threshold voltage distribution of a memory cell, and in particular, of a multi-level memory cell.